Sample-and-hold (S/H) circuits are widely used, for example, to store an analog voltage signal accurately over a time period ranging typically from as little as a few microseconds to as long as several minutes. A S/H circuit may be considered as a switched capacitor network, wherein the input signal is sampled to a sampling capacitor during a sampling time, and is held on the capacitor during the holding time. Since the analog voltage across the sampling capacitor in the hold time should be available at the output terminal of the circuit even under low impedance, an output buffer amplifier is typically connected to the sampling capacitor.
The main desired characteristics of a S/H circuit may be a low hold mode voltage droop, short settling time in the acquisition or sampling mode, a low offset voltage, and hold-mode feedthrough. The hold mode droop is dependent on the leakage current from the sampling capacitor to the various components connected thereto.
In one type of S/H circuit a transmission gate in the form of a field-effect transistor (FET) samples the input voltage onto the sampling capacitor. An output amplifier reads the voltage from the sampling capacitor. The sampling capacitor may also be formed in the same semiconductor substrate as the FET. Accordingly, a parasitic diode may be formed by the body of the FET and the sampling capacitor. The parasitic diode may cause voltage droop or an inaccurate voltage for the output of the S/H circuit.